1. Field of the Invention
The present invention relates generally to high density integrated circuit devices, and more particularly to interconnect structures for multi-level three-dimensional stacked devices.
2. Description of Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking for techniques for stacking multiple levels of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
Also, cross-point array techniques have been applied for anti-fuse memory in Johnson et al., multiple layers of word lines and bit lines are provided, with memory elements at the cross-points. The memory elements comprise a p+ polysilicon anode connected to a word line, and an n-polysilicon cathode connected to a bit line, with the anode and cathode separated by anti-fuse material.
Another structure that provides vertical NAND cells in a charge trapping memory technology is described in “Novel 3-D Structure for Ultra-High Density Flash Memory with VRAT and PIPE” by Kim et al., 2008 Symposium on VLSI Technology Digest of Technical Papers”; 17-19 Jun. 2008; pages 122-123.
In three-dimensional stacked memory structures, vertical interconnects couple various circuit structures of the array to overlying access lines, such as global bit lines and source lines, used for reading and writing the memory cells.
One drawback of conventional three-dimensional stacked memory devices is that the vertical interconnect structures to different portions in the array are formed separately in different levels overlying the array. This requires the creation of a lithographic mask for each level and an etching step for each level. The cost to implement the vertical interconnects increases with the number of lithographic steps needed. In addition, issues such as mask alignment and etch selectivity during manufacturing can reduce yield.
It is desirable to provide a structure for three-dimensional integrated circuit memory with a low manufacturing cost, and high yield.